The invention relates to a system memory constructed with symbol-wide memory chips and having an error protection feature. Developments in memory technology have resulted in storage chips accommodating multiple data bits per memory location in each chip with corresponding multiple outputs. Errors in the storage of data in these memories are generally classified as occurring due to two distinct causes. One is a non-destructive environmental phenomenon caused by impingement of atomic alpha particles. Those particles, present in ordinary background atomic radiation, have energy values vis-a-vis the data signal stored in the cell. When such cells are struck by atomic alpha particles, the binary values stored in the cell may flip to an opposite value. Hence a data error occurs. These errors are therefore transient and usually influence a single bit at a time. These failures at small values of the minimum circuit detail occur relatively often.
The second major cause of error is the actual physical failure of one of the memory components. This failure produces a permanent or "hard" error. In general, the latter category of errors occurs relatively infrequently. On the other hand, such errors can influence any number of bits in a symbol, and therefore have more dramatic impact. Now, usually symbols are 2.sup.i bits wide, wherein i may have values of 1 . . . 4. Furthermore memory chips with symbols of (2.sup.i +1) bits (i.e. 2.sup.i data bits plus one parity bit) have been manufactured, so that on the level of a memory chip a single bit error in a symbol may be detected. The present invention makes use of the latter type of memory chips, while extending the amount of error protection.